The present invention relates to an improved binary calibration technique which is useful for calibrating the timing of control and data signals in memory devices, for example, SLDRAM memory devices.
Memory devices are constantly evolving in the directions of faster speed and higher memory density. To this end, dynamic random access memory (DRAM) devices have evolved from simple DRAM devices to extended data out DRAM (EDO DRAM) to synchronous dynamic random access memory (SDRAM) to double data rate synchronous dynamic random access memory (DDR SDRAM) to SyncLink dynamic random access memory (SLDRAM), the latter of which is the subject of much current industry interest. SLDRAM has a high sustainable bandwidth, low latency, low power, user upgradability and support for large hierarchical memory applications. It also provides multiple independent banks, fast read/write bus turn-around, and the capability for small fully pipelined bursts.
One characteristic of SLDRAM is that it is a double data rate device which uses both the positive- and negative-going edges of a clock cycle to READ and WRITE data to the memory cells and to receive command and FLAG data from a memory controller.
An overview of SLDRAM devices can be found in the specification entitled xe2x80x9cSLDRAM Architectural and Functional Overview,xe2x80x9d by Gillingham, 1997 SLDRAM Consortium (Aug. 29, 1997), the disclosure of which is incorporated by reference herein.
Because of the required high speed operation of SLDRAM, and other contemporary memory devices, system timing and output signal drive level calibration at initialization, including start-up or reset, is a very important aspect of the operation of such devices to compensate for wide variations in individual device parameters.
One of the several calibration procedures which is performed in current SLDRAM devices is a timing synchronization of clock signals CCLK (command clock signal) and DCLK (data clock signal) with data provided on an incoming command path CA and FLAG path (for the CCLK signal) and on the data paths DQ (for the DCLK signal) so that incoming data is correctly sampled. Currently, a memory controller achieves this timing calibration at system initialization by sending continuous CCLK and DCLK transitions on those clock paths and transmitting inverted and non-inverted versions of a 15 bit repeating pseudo random SYNC pattern xe2x80x9c111101011001000xe2x80x9d on each of the data paths DQ, the command path CA, and the FLAG path. The SLDRAM recognizes this pseudo random sequence by two consecutive ones xe2x80x9c1xe2x80x9d appearing on the FLAG bit and determines an optimal internal delay for CCLK and DCLK relative to the data each clocks to optimally sample the known bit pattern. This optimal delay is achieved by adjusting the temporal position of the received data bits to achieve a desired bit alignment relative to the clock. This is accomplished by adjusting a delay in the receiving path of the received data until the received data is properly sampled by the clock and recognized internally. Once synchronization has been achieved, that is, the proper delays on the data receiving paths have been set, the memory controller stops sending the SYNC pattern and the SLDRAM, after all calibrations are completed, can be used for normal memory READ and WRITE access.
In prior synchronizing schemes using a calibration bit pattern as discussed above, all incoming data can properly be aligned with respect to the clock used to latch in the data by adjusting the data delays relative to the clock (CCLK or DCLK) to position a sampling clock edge at or near the center of the data xe2x80x9ceyexe2x80x9d or xe2x80x9cwindowxe2x80x9d where the data is valid on an incoming data path. However, this calibration procedure is independently carried out for each incoming data path, which may take some time and which also may, in extreme cases, cause the data xe2x80x9ceyexe2x80x9d on different incoming data paths to be aligned on different edges of the clock signal.
FIG. 1, for example, shows raw data coming into an SLDRAM module from a memory controller for a representative FLAG data path, and three of the command bus data paths CA less than 0 greater than , CA less than 1 greater than  and CA less than 2 greater than  (there are actually ten such data paths for the exemplary SLDRAM command bus). As shown, data positions arriving on each of the representative FLAG and CA less than 0 greater than , CA less than 1 greater than  and CA less than 2 greater than  data paths are all skewed relative to one another.
When the conventional calibration procedure is performed using the 15 bit pseudo random pattern described above, each of the data bits on each of the incoming data paths is properly serially aligned with an edge of clock signal CCLK, as shown in FIG. 2, for the exemplary data paths FLAG and CA less than 0 greater than , CA less than 1 greater than  and CA less than 2 greater than . That is, the clock edge CCLK is at or near the center of the data xe2x80x9ceyexe2x80x9d or xe2x80x9cwindowxe2x80x9d for each data bit on each data path. However, as is also shown in FIG. 2, it is possible that the data bits in one data path are misaligned, or aligned to an edge of the clock opposite to that of another data path. For example, while the position of data on the CA less than 0 greater than  data path and the data on the FLAG data path are properly aligned with each other, these two are misaligned with respect to the data bits on the CA less than 1 greater than  and CA less than 2 greater than  data paths. Thus, even though serial calibration of each data line relative to the clock CCLK has been achieved, there is still a possibility for misalignment in a parallel direction across all of the data paths.
The present invention provides correct alignment of data entering a memory module, e.g., an SLDRAM module, on a plurality of incoming data paths in both a serial and parallel direction. Serial data alignment is first acquired for one of the incoming data paths, and then the remaining data paths are bit wise aligned in parallel to a previously aligned data path. In this way, serial and parallel calibration of all data paths is achieved. This alignment may be performed, for example, at power-up or reset of the memory device.